Magnetoelectronic devices, also referred to as spin electronics devices or spintronics devices, are used in numerous information technologies, and provide for non-volatile, reliable, radiation resistant, and high-density data storage and retrieval. Examples of magnetoelectronic devices include, but are not limited to, magnetic random access memory (MRAM), magnetic sensors, and read/write heads for disk drives.
Typically, a magnetoelectronic device, such as a magnetic memory element, has a structure that includes multiple ferromagnetic layers separated by at least one non-magnetic layer. Information is stored in a magnetic memory element as the direction of magnetization vectors in the magnetic layers. Magnetization vectors in one magnetic layer, for instance, are magnetically fixed or pinned, while the magnetization direction of the other magnetic layer is free to switch between the same and opposite directions that are called “parallel” and “antiparallel” states, respectively. In response to parallel and antiparallel states, the magnetic memory element represents two different resistances. The resistance has a minimum value when the magnetization vectors of the two magnetic layers point in substantially the same direction, and a maximum value when the magnetization vectors of the two magnetic layers point in substantially opposite directions. Accordingly, a detection of change in resistance allows a device, such as an MRAM device, to detect the information stored in the magnetic memory element.
FIGS. 1A and 1B illustrate a type of magnetic memory element known as a magnetic tunnel junction element in parallel and anti-parallel states, respectively.
As shown, a magnetic tunnel junction (MTJ) element 100 can be formed from two magnetic layers 110 and 130, each of which can hold a magnetic field, separated by an insulating (tunnel barrier) layer 120. One of the two layers (e.g., fixed layer 110), is set to a particular polarity. The other layer's (e.g., free layer 130) polarity 132 is free to change to match that of an external field that can be applied. A change in the polarity 132 of the free layer 130 will change the resistance of the MTJ element 100. For example, when the polarities are aligned (FIG. 1A), a low resistance state exists. When the polarities are not aligned (FIG. 1B), a high resistance state exists. The illustration of MTJ 100 has been simplified and those skilled in the art will appreciate that each layer illustrated may comprise one or more layers of materials, as is known in the art.
In contrast to conventional RAM technologies which store data as electric charges or current flows, MRAM uses magnetic elements such as MTJ 100 to store information magnetically. MRAM has several desirable characteristics that make it a candidate for a universal memory, such as high speed, high density (i.e., small bitcell size), low power consumption, and no degradation over time. However, MRAM has scalability issues. Specifically, as the bit cells become smaller, the magnetic fields used for switching the memory state increase. Accordingly, current density and power consumption increase to provide the higher magnetic fields, thus limiting the scalability of the MRAM.
Unlike conventional MRAM, Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) uses electrons that become spin-polarized as the electrons pass through a thin film (spin filter). STT-MRAM is also known as Spin Transfer Torque RAM (STT-RAM), Spin Torque Transfer Magnetization Switching RAM (Spin-RAM), and Spin Momentum Transfer (SMT-RAM). During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer. The read operation is similar to conventional MRAM in that a current is used to detect the resistance/logic state of the MTJ storage element, as discussed in the foregoing. As illustrated in FIG. 2A, a STT-MRAM bit cell 200 includes MTJ 205, transistor 210, bit line 220 and word line 230. The transistor 210 is switched on for both read and write operations to allow current to flow through the MTJ 205, so that the logic state can be read or written.
Referring to FIG. 2B, a more detailed diagram of a STT-MRAM cell 201 is illustrated, for further discussion of the read/write operations. In addition to the previously discussed elements such as MTJ 205, transistor 210, bit line 220 and word line 230, a source line 240, sense amplifier 250, read/write circuitry 260 and bit line reference 270 are illustrated. As discussed above, the write operation in an STT-MRAM is electrical. Read/write circuitry 260 generates a write voltage between the bit line 220 and the source line 240. Depending on the polarity of the voltage between bit line 220 and source line 240, the polarity of the free layer of the MTJ 205 can be changed and correspondingly the logic state can be written to the cell 201. Likewise, during a read operation, a read current is generated, which flows between the bit line 220 and source line 240 through MTJ 205. When the current is permitted to flow via transistor 210, the resistance (logic state) of the MTJ 205 can be determined based on the voltage differential between the bit line 220 and source line 240, which is compared to a reference 270 and then amplified by sense amplifier 250. Those skilled in the art will appreciate the operation and construction of the memory cell 201 is known in the art.
Additional details are provided, for example, in M. Hosomi, et al., A Novel Nonvolatile Memory with Spin Transfer Torque Magnetoresistive Magnetization Switching: Spin-RAM, proceedings of IEDM conference (2005), which is incorporated herein by reference in its entirety.
A key challenge in embedding STT-MRAM into sub-100 nm CMOS logic devices is to integrate the MTJ stack (e.g., layers 110, 120, and 130 collectively) with common Back-End-Of-The-Line (BEOL) interconnects, such as contacts, insulators, metal levels, bonding sites for chip-to-package connections, etc., without substantially impacting yield and reliability. The problem is that the MTJ may be damaged during BEOL processing, or that mobile ions and other contaminants related to the MTJ can degrade BEOL inter-level dielectrics (ILDs). Integration is particularly challenging when the MTJ is disposed with fine-pitch interconnects (e.g., to achieve smaller memory cells) in conjunction with the ILDs common to sub-100 nm CMOS devices.
The MTJ needs to not only form and comply with specified characteristics throughout the manufacturing steps, but also function reliably. In addition, the incorporation of various materials used for the MTJ need to not adversely affect the BEOL interconnects.
That is, there should be relatively few or no mobile ions or contaminants allowed into BEOL ILDs.